/*
 * Copyright (c) 2004-2005 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Jin Yinghan
 */

#ifndef __CPU_EDGE_HYST_TYPE_HH__
#define __CPU_EDGE_HYST_TYPE_HH__

#include <vector>

#include "base/types.hh"
#include "config/the_isa.hh"
#include "arch/isa_traits.hh"
#include "cpu/edge/pred/base_predictor.hh"

template<class Impl>
class HysteresisTypeP : public BasePredictor<Impl>
{
  private:
    typedef TheISA::ExitID ExitID;
    typedef TheISA::ExitType ExitType;

    enum HystIndexMode {
        Address,
        AddressAndExit,
        AddressAndPath,
        AddressAndHist,
        AddressAndPredication,
        InvalidIndexMode
    };

    enum TableMode {
        NormalTable,
        AliasFree,
        InvalidTableMode
    };

    struct HystEntry
    {
        HystEntry(BasePredictor<Impl> * ptr) :
            branchType(TheISA::seq),
            hyst(false),
            updated(false)
        {}

        ExitType branchType;
        bool hyst;
        bool updated;
    };

  public:
    HysteresisTypeP(DerivEdgeCPUParams * params) :
        BasePredictor<Impl>(params),
        hystTable(this, (params->hystBTypeTableMode == "AliasFree") ?
                  true : false)
    {}

    ~HysteresisTypeP() {}

    void init(unsigned numEntries, unsigned blockShiftAmt,
            std::string index_mode, std::string table_mode, bool exclude_seq);

    void reset();

    ExitType lookup(Addr block_pc, int addr_space_id, ExitID exit_id,
            uint64_t path_hist, uint64_t hist, uint64_t predication_hist);

    void update(Addr block_pc, int addr_space_id, ExitID exit_id,
            uint64_t path_hist, uint64_t hist, uint64_t predication_hist,
            ExitType branch_type);

    int getCounterBits() {
        panic("Unimplemented func: getCounterBits.\n");
    }

  private:

    HystIndexMode indexMode;

    TableMode tableMode;

    unsigned idxGen(Addr PC, int addr_space_id, ExitID exit_id,
            uint64_t path_hist, uint64_t hist, uint64_t predication_hist);
 
    PredictorTable<HystEntry, Impl> hystTable;

    unsigned numEntries;

    unsigned idxLength;

    unsigned idxMask;

    unsigned blockShiftAmt;
};

#endif //_CPU_EDGE_HYST_TYPE_HH
